Intel has just teased its upcoming Xe architecture powered GPUs which come in three distinct packages. The three Xe GPUs were teased by Raja Koduri who gave a visit to the Xe GPU Lab in Folsom, California.
Intel Teases Three Massive Xe GPUs In BFP “Big Fabulous Package” Flavors – Coming To A Data Center Near You Soon!
From Xe LP to Xe HPC, Intel is developing all sorts of GPUs which will go on to power its next-gen graphics portfolio. At the helm of these products would be the Xe HP and Xe HPC powered GPUs which will be featured in machines with up to exaflops of compute power. Intel already gave us a glimpse of one of their Xe HP GPU a while back when Raja Koduri posted about a celebration back in December 2019 which marked a significant milestone in the development of the largest silicon in Bangalore, India.
Raja Koduri showcases test boards for Intel’s DG1 Xe-LP and Xe HPC GPUs running pre-release silicon!
But even that massive chip with a package size exceeding 3500mm2 is nothing compared to what Raja has teased us today. For starters, there are three distinct GPU packages that Raja has teased including the Xe HP package we got to see earlier accompanied by a smaller die & a super-massive one which eclipses the other two chips.
Based on our exclusive report and from what Intel has talked about in regards to its Ponte Vecchio chip, it looks like Intel in all onboard the MCM train with each chip consisting of several Xe GPU tiles that will be interconnected together to form a monster of a GPU. Here are the actual EU counts of Intel’s various MCM-based Xe HP GPUs along with estimated core counts and TFLOPs:
Xe HP (12.5) 1-Tile GPU: 512 EU [Est: 4096 Cores, 12.2 TFLOPs assuming 1.5GHz, 150W]
Xe HP (12.5) 2-Tile GPU: 1024 EUs [Est: 8192 Cores, 20.48 assuming 1.25 GHz, TFLOPs, 300W]
Xe HP (12.5) 4-Tile GPU: 2048 EUs [Est: 16,384 Cores, 36 TFLOPs assuming 1.1 GHz, 400W/500W]
In the two shots above, you can see actual test boards equipped with the Xe powered DG1 and the Xe HPC GPUs. You can clearly see that the DG1 GPU is referred to ES1 which means that this unit is from an early test kit and also mentions 12×8 which equals 96. The DG1 GPU based on Xe LP micro architecture is going to feature 96 EUs and this could be the flagship variant that is being tested. In the other picture, you can see an even more interesting part which reads ATS-4T. This is the largest of the three chips pictured above and from the looks of it, it refers to the chip being internally code-named Arctic Sound and the 4T could possibly refer to the 4-tile MCM design which I’ve mentioned above.
Once again, Raja has stationed a single AA battery for scale and we will definitely provide a more in-depth article on the specific package sizes of the other two chips in a follow-up article. Raja Koduri also makes use of a new and interesting terminology to define the massive size of its Xe HP and Xe HPC parts referred to as BFP or Big Fabulous Package. The first system to utilize the Xe HPC GPUs will be the Aurora Supercomputer which will be deployed in 2021 and will be the lead 7nm product from Intel to enter the tech landscape.
The Intel Xe GPU architecture is one scalable architecture powering various products. Intel is planning to offer three microarchitectures derived from Xe. These include:
Intel Xe LP (Integrated + Entry / Mainstream Gaming)
Intel Xe HP (Enthusiast, Workstation / Datacenter / AI)
Intel Xe HPC (HPC Exascale)
While HPC would be first to use 7nm Xe GPUs, Intel’s 10nm Xe GPU lineup would be making its way to the mainstream and enthusiast gaming market in 2020 which would be utilizing the consumer-tuned Xe LP architecture. Intel recently gave us the first demo of its Xe LP GPU inside its upcoming Tiger Lake CPUs which is proving to be a major leap in integrated graphics performance for Intel as seen in the demonstration. Expect more information on the Xe HP & Xe HPC GPUs in the coming months.